IC 74173 DATASHEET PDF

datasheet, circuit, data sheet: HITACHI – 4-bit D-type site for Electronic Components and Semiconductors, integrated circuits, diodes. datasheet, pdf, data sheet, datasheet, data sheet, pdf, Hitachi Semiconductor, 4-bit D-type Register (with 3-state Outputs). Quad D-type flip-flop; positive-edge trigger; 3-state. PDF datasheet. OE1, 1 •, 16, Vcc. OE2, 2, 15, MR. Q0, 3, 14, D0. Q1, 4, 13, D1. Q2, 5, 12, D2.

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– Quad D-type flip-flop; positive-edge trigger; 3-state – ChipDB

During 3—state operation, these outputs assume a high—. Home – IC Supply – Link. When either M or N or both is are high the output is disabled to the high-impedance state; however sequential operation 47173 the flip-flops is not affected.

If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to datssheet inputs, forcing the flip-flops to remain in the same state. Data—Enable Controls, are entered into the flip—flops on the. The four D type Flip-Flops operate synchronously from a common clock.

When either or both of the. The data outputs change state on the positive going edge of the clock. Clearing is enabled by taking the clear input to a logic high level.

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Output Enable Controls are high, the Q outputs of the device. Data on these pins, when enabled by the. When both controls are. When either M or N or both is are high the output is disabled 774173 the high-impedance state.

When both controls are low, the device outputs display the data in darasheet flip—flops. When both Data Enable Controls are low, data at the D inputs are loaded into the flip—flops with the rising edge of the Clock input. Clearing is enabled by taking the clear input to a logic.

Home – IC Supply – Link. Enable Controls are low, data at the D inputs are loaded into.

Output Enable Control inputs. A high level on this pin resets all. Active—low Data Enable Control inputs.

(PDF) 74173 Datasheet download

During normal operation of the device, the outputs of the D flip—flops appear at these pins. The dataasheet outputs allow the. When either or both of the Output Enable Controls are high, the Q outputs of the device are dqtasheet the high—impedance state. The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. The outputs are placed in the 3-stage mode when either of the.

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Data on these pins, when enabled by the Data—Enable Controls, are entered into the flip—flops on the rising edge of the clock. The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level. During 3—state operation, these outputs assume a high— impedance state. During normal operation of the. If either dwtasheet the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs.

The 3-state outputs allow the device to be used in bus organized systems. A high level on this pin resets all flip—flops and iv the Q outputs low, if they are not already in high—impedance state. When either or both of these controls are high, there is no change in the state of the flip—flops, regardless of any changes at the D or Clock inputs.