74HC Datasheet, 74HC stage Binary Counter Datasheet, buy 74HC, 74HC pdf, ic 74HC description/ordering information. The ‘HC devices are stage asynchronous binary counters, with the outputs of all stages available externally. A high. Data sheet acquired from Harris Semiconductor. SCHSD. Features. • Fully Static Operation. • Buffered Inputs. • Common Reset. • Negative.

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I started with the VHC part this time: That should relax some timing as your MSB are no longer rely on the propagation from the lower bits. Doesn’t look promising – although the typical 21ns 6V or 25ns 4.

Musta been a bunch of pixie-dust in there, or a poor memory of 18 years ago. Maybe a fast external counter for the lowest 4 or 8 bits, and the PIC generates the upper ones? Synchronization is an issue, but it’s worth thinking about – maybe if the PIC runs from the external Sign up Already a member?

Maybe I’m doing this wrong? The clock input on the ‘ works on the positive edge, so the schematic above changes a bit, but at least the addresses seem OK.

Interesting discovery upon looking back Synchronous Counters Synchronous counters use extra logic to form the next state from the previous one directly, without waiting for clocks to ripple through, so the outputs settle faster. I’m using typical values for the moment; if it doesn’t work there, it’s not going to work worst-case, either. I’ll have to give that one some thought. I’m already bummed about the color thing What about using the fastest PIC available and bitbanging the address lines?


Monitors can handle some clock frequency variations. Datashee I were going to build a bunch of these, I’d try harder to get the 74HC to work.

This also ignores the fact that two 74HCs need to be chained to generate the bit address: I have to go take them out of my shopping cart now: VHC to the rescue? In the store-each-dot-period-as-a-byte plan, this is trivial – I have full and easy control of all 74hd4040 singals on on a per-dot basis. So, with two of them connected to generate 19 bits of address, the tpd from the clock edge to the MSB settling is: For Qd the datasheey bitthe typical tpd is given as 8.

74HC4040 Datasheet PDF

Surely the 74VHCwith its Mhz typical max clock frequency will do the job! If I’m reading the datasheet correctly, the maximum delay from clock edge to valid outputs is Let’s run the numbers, using a 15pF load: Since it’s a ripple counter, Q0 flips, then Q1, then Q2, etc, so we have to add all the delays so see how long it takes for the address to settle to the next value.

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All these numbers involving multiples of propagation-delays are making me question even further how I got the ol’ LCD controller running. Yeah, I had read about keeping video blanked outside of the active area.

74HC data sheet datasheet & applicatoin notes – Datasheet Archive

Now, I need 5 ICs to make the counter – if it’s even fast enough. Did I miss something on the ripple counters? I spent the afternoon re-working my ugly SOIC adapter board designs to reduce the ground-connection impedance and add on-board bypass caps.

I haven’t used VHC logic before, but keep seeing it around. Interestingly, it also has a synchronous clear, and connections for synchronous expansion between counters with lookahead carry outputs. They’re not completely general anymore, since now they 74hc0440 standard corner pin supply connections, but they should be better for signal integrity.

This could be interesting. I need 5 of them, which sucks. The dot clock is Yes, delete it Cancel.